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INTEGRATED CIRCUITS
DATA SHEET
SAA7500 Digital satellite radio broadcasting tuner decoder (SAT-2)
Product specification File under Integrated Circuits, IC01 September 1989
Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
GENERAL DESCRIPTION The SAA7500 performs a decoder function for digital satellite sound broadcasting tuners. It is designed to decode one of 16 stereo channels broadcasting audio signals in accordance with the German standard Technische Richtlinie ARD/ZDF Nr. 3R1. Features * Clock recovery * Differential decoding QUICK REFERENCE DATA PARAMETER Supply voltage Power dissipation Clock frequency PACKAGE OUTLINE Ptot T20N 20.48 SYMBOL VDD 4.5 MIN. 5.5 500 MAX. * Main frame synchronization
SAA7500
* Swapping half-frames in case of inversion * Unscrambling * Demultiplexing * Subframe synchronization * Error correction and concealment * Scale factor decoding with error correction * Shift into the original values using the scale factors * Mute in case of synchronization loss
UNIT V mW MHz
68-lead plastic leaded chip carrier (PLCC); `pocket' version (SOT188AA); SOT188-2; 1996 September 05.
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
SAA7500
September 1989
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Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
PINNING
SAA7500
Fig.2 Pinning diagram; for pin functions see next page.
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
Pin functions (1) = CMOS level input. (2) = TTL level input. (3) = CMOS level input with pull down resistor. PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24-33 34 35-40 41 42 43 44 45 46 47 48 MNEMONIC LZA LZB LZC STO T20N LZD LZE PHD LZF KUS SYLN PD PC PB PA UPMU INTR TUP PAUP R32 L32 DWCA DWCB B16-7 VSS1 B6-1 OOSC ACM AWD AWT AWR AMUN DIC DIE I(3) I(3) I(3) I(3) I(1) I(3) I(3) O I(3) O O I(2) I(2) I(2) I(2) I(2) O O O O O I(3) I(3) O I O O O O O O O O O DESCRIPTION phase adjustment for the internal clock. phase adjustment for the internal clock. phase adjustment for the internal clock. control input for testing. 20.48 MHz clock input from voltage controlled oscillator (VCX). control input for testing. control input for testing. phase control signal for VCX. control input for testing. test output (A'B' swap). synchronization indication flag. programme number input selector (MSB). programme number input selector. programme number input selector. programme number input selector (LSB). mute input (controlled by microcomputer). interrupt flag for microcomputer. programme type interface (clock). programme type interface (data). multiplex control signal for right channel. multiplex control signal for left channel. DA-converter mode select input. DA-converter mode select input. audio data for parallel interface, bits 16 (LSB) to 7. ground (supply). audio data for parallel interface, bits 6 to 1 (MSB). 4.096 MHz clock output. concealment flag (for SAA7220P/C). audio data (for SAA7220P/C). bit clock (for SAA7220P/C). word select signal (for SAA7220P/C). mute signal (for SAA7220P/C). data output for testing. data output for testing.
SAA7500
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
PIN NO. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 MNEMONIC TFKN M2N M1N PID PIF PITN n.c. ASC BSC FSY T10N n.c. SWA VSS2 SWB MCR ST1 ST2 ST3 VDD I(2) I I(2) I(1) I(3) I(3) I(3) I O O O O O I(2) I(2) O O O burst clock for test data. channel mode select input. channel mode select input. programme information (PI) interface output (data). programme information (PI) interface output (window signal). programme information (PI) interface output (clock). not connected. data output for 10.24 Mbit/s interface. data output for 10.24 Mbit/s interface. window signal for 10.24 Mbit/s interface. 10.24 MHz clock output. not connected. 10.24 Mbit/s data input. ground (screen). 10.24 Mbit/s data input. master reset. control input for testing. control input for testing. DESCRIPTION
SAA7500
control input for testing and mode select for 10.24 Mbit/s interface. power supply.
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
FUNCTIONAL DESCRIPTION General
SAA7500
The SAA7500 has been designed to decode 16 stereo channel sound broadcasting signals in accordance with the German standard - Technische Richtlinie ARD/ZDF Nr. 3R1. The channel carrying the sound broadcast programme is selected and converted into an intermediate frequency by a frontend. The signal is then amplified and demodulated (4 PSK (Phase Shift Keying) with carrier recovery). The outputs from the demodulator are two differential coded signals that are input into the SAA7500. The SAA7500 decoder outputs the audio data, of the selected stereo or mono channel, as linear quantized 16-bit audio samples. Selection of the desired audio channel, as well as stereo or mono mode, is controlled by inputs PA, PB, PC and PD. These inputs may be driven directly by switches or controlled by a microcomputer. When under the control of a microcomputer, the SAA7500 transmits serial data to the microcomputer on the type of programme (16 stereo or 32 mono). The corresponding synchronization of the subframe is partly performed by the SAA7500 (every 2 ms) and at a higher level by the microcomputer (every 16 ms). The SAA7500 also sends to the microcomputer, programme information code data together with its clock and window signal. The circuit automatically performs the system error correction and concealment. In the transmit error rate range of 0 to 3 x 10-3 a theoretical C/N (carrier-to-noise ratio) gain of about 6 dB is obtained. The residual error rate is nearly zero for transmit error rates 3 x 10-4. The remaining functions, such as clock recovery, main and subframe synchronization and scale factor decoding, are protected in a similar manner so that they will not influence the residual error rate. Clock recovery The baseband signals A' and B' are connected to the SWA and SWB inputs of the SAA7500. For clock recovery, the phase of the incoming data streams is compared with T10N (half the oscillator frequency). The output of the phase comparator (PHD) controls, by means of the loop filter, the voltage controlled oscillator (both are external to the IC) and thus its output signal T20N. For energy dispersal, for example, in modulation pauses or with constant signals, the data streams are scrambled during generation. The exceptions are the synchronization words and the special service bits. In order that the phase correspondence between the recovered system clock (T10N) and the input signals A' and B' can be adjusted to a minimum bit error rate (BER), a programmable phase shifter is provided (inputs LZA, LZB, LZC and ST3). The differential decoder logic delivers the original data streams which may be exchanged depending on the number of mixer stages on the transmission channel. The polarity of the two synchronization words will indicate if this is necessary, if so the two data streams will be automatically switched over. Synchronization Using the synchronization circuit, the incoming data streams are first searched for 11-bit Barker codewords. The synchronization circuit permits two errors for both synchronization words, which guards against failure of the synchronization word. If the synchronization word has been detected, the following data is examined at frame length intervals to see if the synchronization word is repeated. If it is repeated, it is acknowledged as a synchronization word (window check) and an internal frame pulse generator takes over further control. There is also synchronization word failure control which initiates a renewed synchronization word search and mutes the AF output if four successive synchronization word failures occur. To enhance the performance the result from the error correction circuit is used as an additional input to the synchronization circuit. This is to avoid extra errors through synchronization loss in the case of relative high, but for reception acceptable, bit error rates. This will not affect the rapid detection of a very high bit error rate or the non-synchronization of the data stream. The decoder will function correctly with a bit error rate up to 3 x 10-3.
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
Demultiplexer
SAA7500
After synchronization, the beginning of a frame is marked and the digital signals are defined as to their assignment. First the non-scrambled special service bit from the half frame A is taken out. The rest of both half frames are unscrambled and demultiplexed so that each half frame is split into two substreams with a rate of 5.12 Mbit/s (see Technische Richtlinie ARD/ZDF Nr. 3R1, main frame specification). Using the inputs from the synchronization circuit and the programme selector (inputs PA, PB, PC and PD) the demultiplexer locks on to the selected programme block and generates all the control signals required for further signal processing. Error correction The error correction circuit provides for exact identification of two errors in a 63/44 BCH block and correction of the incorrect bits. In the event of more than two errors the identification circuit can identify incorrect BCH blocks with up to five errors. The BCH block is operated on by a syndrome calculator, the results controls the lines of an error correction matrix. The output of this matrix corrects (inverts) the incorrect bits when data is shifted out from its buffer. The BCH block is then fed through a second syndrome calculator. In the event of more than two errors the result of the whole calculation will be other than zero. This information provides the concealment in the next stages. The two adjacent samples related to the detected incorrect sample are added and divided by two, the result replaces the incorrect sample (interpolation). In the event of successive bad samples the last corrected sample is held until a good sample is detected (hold function). A high error frequency in the event of synchronization loss will activate the muting function and set the output data to zero. This information, if concealment is not active, is used in the synchronization circuit as described in that section. When the samples are correct it can be assumed that the synchronization is also correct. Scale factor, programme type evaluation and shift sunction The transmitted samples are returned to their original range of values by the scale factor, which is obtained by decoding the ZI-subframe. The start of this frame is coupled to the start of the special services frame, synchronization for this frame uses the same principle as for the main frame. In the scale factor evaluation unit the BCH 14/6 code words (three times transmitted) are fed into a majority selection circuit working at bit level. Subsequently the error check and the correction of a maximum of two errors is carried out. The SAA7500 contains the synchronization word detection and error check for the subframe synchronization word with its repetition time of 2 ms. The programme type evaluation with its superior synchronization has to be performed external to the chip, for example, by a microcomputer. For this purpose data is available in 8-bit blocks at a serial interface (INTR, PAUP and TUP; block rate = 4000/s). The same microcomputer can also perform the programme selection (inputs PA, PB, PC and PD). At the input to the concealment buffer the corrected 11 bits (MSB) are combined with the 3 unprotected transmitted bits (LSB). The scale factor determines the required shift-back operations needed to convert the transmitted values back into the original values. Voids that occur are filled with noughts or ones corresponding to the sign bit. The shift-back and filling of voids ensures that no incorrect bits occur above the range defined by the scale factor. The upper 16 bits represent the regenerated audio sample.
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
Digital-to-analogue conversion and interfaces
SAA7500
The SAA7500 enables different DAC systems to be used. For control of the SAA7220P/C and TDA1541 a 2.5 external divider must be connected to the 20.48 MHz clock signal to produce the required 8.192 MHz clock signal. A serial interface is built in with the following outputs: bit clock (AWT), word select (AWR) and audio data (AWD). In addition the mute signal (AMUN) and the concealment flag (ACM) are also available. The SAA7220P/C and TDA1541 are equipped with a digital audio interface for domestic use equivalent to `IEC proposal No. 84 (secretariat 28; from June 1985)'. For DACs with a parallel interface in a multiplex mode the audio data are available at the B1(MSB)-B16 outputs. The multiplexing is controlled by the L32 and R32 outputs. Using the mode outputs DWCA and DWCB the code (offset binary or two's complement) and polarity can be selected. Additional information, including the scale factor is available through the programme information (PI) interface (PID, PITN, and PIF). Another interface, using the ASC, BSC and T10N outputs, makes available signals from the differential decoder. These signals are used for bit error measurement and an optimized phase adjustment of the internal clock (refer to `clock recovery' section). An optional application of the control signals for mute and concealment operations is possible using the outputs AMUN and ACM. For the mute signal a different time relationship to the unwanted pulse with very low C/N values may be obtained. The external application of the concealment signal is recommended; if an additional interpolation is required between additional samples with different levels in the external circuitry (such as the SAA7220P/C). Truth tables Table 1 Delay adjustment pins 1 to 3 LZC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LZB 0 1 0 1 0 1 0 1 LZA 4x 3x 2x 1x 0x -1 x -2 x -3 x 0 1 DELAY Table 2 pin 64 Master reset MCR 0 1 Table 3 pin 16 Mute UPMU no yes FUNCTION FUNCTION operation master reset
1.5 x gate delay time (NAND)
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
Table 4 Programme number pins 12 to 15 PD 0 0 0 . 1 1 1 Table 5 pin 8 PC 0 0 0 . 1 1 1 PB 0 0 1 . 0 1 1 0 1 0 . 1 0 1 PA 1 2 3 . 14 15 16 Table 10 Concealment pin 42 ACM Phase control signal PHASE lead phase lag phase Synchronization indication SYLN 0 1 Table 7 pin 67 ST3 0 1 DATA ASC/BSC after unscrambler before unscrambler no Mode select for data outputs ASC and BSC for 10.24 Mbit/s interface SYNCHRONIZATION yes Table 12 Interrupt pin 47 INTR 0 1 no yes Table 11 Mute pin 46 AMUN Table 6 pin 11 0 1 yes no 0 1 no yes PROGRAMME NO. 0 0 1 1 Table 9 Channel mode select pins 50 and 51 M2N 0 1 0 1 M1N
SAA7500
CHANNEL MODE mono (1 + 2) mono R(2) mono L(1) stereo
FUNCTION
PHD 0 1
MUTE
INTERRUPT
Table 8 Data converter mode select B1 (MSB) to B16 pins 22 and 23 DWCB 0 0 1 1 0 1 0 1 DWCA DA CONVERTER MODE compl. offset binary offset binary compl. 2's complement 2's complement
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
RATINGS Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) PARAMETER Supply voltage range Input voltage range(1) Input current Output current Supply current in VSS Supply current in VDD Total power dissipation Operating ambient temperature range Storage temperature range Note 1. VDD + 0.5 must not exceed 7.0 V. HANDLING VDD VI II IO ISS IDD Ptot Tamb Tstg SYMBOL -0.5 -0.5 - - - - - -25 -55 MIN. 7.0 VDD+0.5 10 10 28 28 500 +85 +150 MAX.
SAA7500
UNIT V V mA mA mA mA mW C C
Inputs and outputs are protected against electrostatic charge in normal handling, however, to be totally safe it is desirable to take normal precautions appropriate to handling MOS devices (see Handling MOS Devices). The PLCC-68 package can only be guaranteed with soldering temperatures up to a maximum of 235 C.
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
DC CHARACTERISTICS Tamb = 0 C to + 70 C; unless otherwise specified PARAMETER Supply voltage Supply current Quiescent supply current Inputs I(1) Input voltage LOW Input voltage HIGH Input current LOW Input current HIGH Inputs I(2) Input voltage LOW Input voltage HIGH Input current LOW Input current HIGH Inputs I(3) Input voltage LOW Input voltage HIGH Pull down resistor Outputs O Output voltage LOW Output voltage HIGH Notes to DC characteristics 1. Tamb = 25 C, all inputs at VSS or VDD, all outputs open. 2. At 25 C max. 1 A. -IOL = 1 mA IOH = 1 mA VOL VOH - 4.0 - - 0.5 - VIL VIH RI - 0.7 VDD 25 - - 50 note 2 note 2 VIL VIH -IIL IIH - 2.0 - - - - - 0.8 - 10 10 note 2 note 2 VIL VIH -IIL IIH - 0.7 VDD - - - - - - Fig.10 note 1 CONDITIONS SYMBOL VDD IDD IDDq 4.5 - - MIN. - 12.5 - TYP. 5.5 - 50
SAA7500
MAX.
UNIT V mA A
0.3 VDD - 10 10
V V A A
V V A A
0.3 VDD - 100
V V k
V V
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
AC CHARACTERISTICS Tamb = 0 to + 70 C; unless otherwise specified PARAMETER T20N clock pulse Pulse width HIGH Pulse width LOW T20N pulse period Data input timing Set-up time for data SWA and SWB to T10N T10N pulse period TPSW Main frame timing Main frame sync pulse Audio data timing Audio sample repetition time Load pulse width HIGH Audio data hold I2S timing Fig.7 fAWT tSAMP Fig.8 fPITN tPITN tPIFH tZI Fig.9 tINTR tPINH - - 250 31.25 - - - - - - 32 31.25 22tPITN 2 - - - - - - 1.024 31.25 - - Fig.6 tSAMP tLPH tADH - - - 31.25 6.25 1 note 1 note 2 Fig.5 tSYNC - 11tP10 - tSWL tP10 - - 50 97.6 - - Fig.4 CONDITIONS Fig.3 tWH tWL tP20 15 15 48 20 22 48.8 - - - SYMBOL MIN. TYP.
SAA7500
MAX.
UNIT
ns ns ns
ns ns
ns s s s
Frequency AWT signal Audio sample repetition time PI interface timing Frequency PITN signal PITN pulse period PIF pulse width HIGH PIF pulse period Output timing Programme type interface INTR pulse period INTR pulse width HIGH Notes to the characteristics
MHz s
kHz s s ms
s s
1. Due to noise, the period tSWL may occasionally vary between 30 and 70 ns. 2. Due to noise, the period time tPSW may occasionally vary between 77.6 and 117.6 ns.
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
SAA7500
Fig.3 Waveform at clock input T20N (pin 5).
Fig.4 Data input timing (pins 59, 61 and 63).
Fig.5 Output timing for 10.24 Mbit/s interface (pins 56, 57, 58 and 59).
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
SAA7500
Fig.6 Audio data timing parallel out (pins 40 to 35, 33 to 24, 21 and 20).
Fig.7 Inter-IC Sound (I2S) timing and mute and interpolation flags (pins 42 to 46).
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
SAA7500
Fig.8 PI interface timing (pins 52 to 54).
(1) Programme type - left (2) Programme type - right (3) This time is approximately 10 s
Fig.9 Output timing programme type interface (pins 17 to 19).
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
SAA7500
Fig.10 Application proposal.
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7500
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C.
SAA7500
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
September 1989
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Philips Semiconductors
Product specification
Digital satellite radio broadcasting tuner decoder (SAT-2)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7500
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
September 1989
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